`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/01/03 15:54:45
// Design Name: 
// Module Name: div
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
//module div(
//    input wire[31:0] a,
//    input wire[31:0] b,
//    input wire is_sign,
//    input wire star,
//    output wire[31:0] hi,
//    output wire[31:0] lo
//);
//    assign hi=32'b0;
//    assign lo=32'b0;
    
//endmodule

module div(
    input clk,
    input wire[31:0] a,
    input wire[31:0] b,
    input wire [1:0]control,
    output wire[31:0] hi,
    output wire[31:0] lo,
    output wire stall
    );
    reg [3:0]star; //3: ce_un, 2: sclr_un, 1: ce_sign 1: sclr_sign
    wire [31:0] unsign_hi,unsign_lo,sign_hi,sign_lo;
    wire stallend,unsign_stallend;
    sign_div signdiv(clk,star[1],star[1],a,star[1],b,stallend,{sign_hi,sign_lo});
    div_gen_0 unsigndiv(clk,star[3], a, star[3], b, unsign_stallend, {sign_hi,sign_lo});



    always @(*) begin
        star<= 4'b0101;
        case(control)
            2'b10: star<= 4'b1001; 
            2'b11: star<= 4'b0110; 
            default: star<=4'b0101;
        endcase
    end
    assign hi=control[1]? control[0]? sign_hi:unsign_hi
                            :32'b0;
    assign lo=control[1]? control[0]? sign_lo:unsign_lo
                            :32'b0;
    assign stall = control[0]? control[1]&~stallend
                                :control[1]&~unsign_stallend;
endmodule
